Donggyu Kim

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Now, I work at Apple. I recieved my Ph.D. from Computer Science at UC Berkeley in 2019, co-advised by Krste Asanović and Jonathan Bachrach. My research interests are in hardware design methodologies including computer architecture, performance/power/energy analysis, and hardware verification.

Publications

Power/Energy Modeling

• Donggyu Kim, Jerry Zhao, Jonathan Bachrach, and Krste Asanović, “Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection”, The 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52), Columbus, OH, October 2019. [Paper] [Slides] [Poster] [Code]
• Donggyu Kim, Adam Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, Krste Asanović, “Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL”, The 43rd International Symposium on Computer Architecture (ISCA-2016), Seoul, Korea, June 2016. [Paper] [Slides] [Code] IEEE Micro’s Top Picks Honorable Mention

Hardware Verification/Debugging

• Vighnesh Iyer, Donggyu Kim, Borivoje Nikolic and Sanjit Seshia, “RTL Bug Localization Through Specification Mining”, 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, San Diego, CA, October, 2019.
• Kevin Laeufer, Jack Koenig, Donggyu Kim, Jonathan Bachrach, Koushik Sen, “RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs”, 2018 International Conference on Computer-Aided Design (ICCAD-2018), San Diego, CA, November 2018. [Paper]
• Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanović, “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”, The 28th International Conference on Field Programmable Logic & Applications, Dublin, Ireland, August 2018. [Paper]
• Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanović, “Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud”, The Second Workshop on Computer Architecture Research with RISC-V (CARRV), Los Angeles, CA, June 2018. [Paper]

FPGA-Accelerated RTL Simulation

• Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, IEEE Micro 39(3), May/June 2019. [PDF] Special Issue: Top Picks from Computer Architecture Conferences
• David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović, “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2019), Seaside, California, February 2019. [PDF]
• Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, International Symposium on Computer Architecture (ISCA-2018), Los Angeles, CA, June 2018. [PDF] One of IEEE Micro’s Top Picks
• Donggyu Kim, Christopher Celio, David Biancolin, Jonathan Bachrach, Krste Asanović, “Evaluation of RISC-V RTL with FPGA-Accelerated Simulation”, The First Workshop on Computer Architecture Research with RISC-V (CARRV), Boston, MA, October 2017. [PDF][Slides][Code]

Hardware Generator/RTL Compiler

• Adam Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, Jonathan Bachrach, “Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations”, 2017 International Conference on Computer-Aided Design (ICCAD-2017), Irvine, CA, November 2017. [PDF]
• Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman, “The Rocket Chip Generator”, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016. [PDF]

Theses

• Donggyu Kim, “FPGA-Accelerated Evaluation and Verification of RTL Designs”, Ph.D. Thesis, University of California, Berkeley, May 2019. [PDF]
• Donggyu Kim, “Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL”, M.S. Thesis, University of California, Berkeley, November 2016. [PDF]

Teaching

I designed various class projects while TA’ing.

• CS152: Computer Architecture and Engineering, Spring 2018
  • FPGA-accerated RTL simulations in Amazon F1 instances
  • Vectorize programs using the RISC-V Vector ISA
• CS61C: Great Ideas in Computer Architecture Spring 2015
  • Paralleize Deep Learning Training Algorithm with Spark [Intro] [Part1] [Part2] [Code]

Misc

New to Chisel? Don’t be afraid. Go check out RISC-V mini.